Fuses are commonly incorporated into semiconductor constructions. The fuses are typically provided as fuse “links”, which are narrow lines in a patterned conductive layer. The links are arranged in vectors or arrays, with the separation between the fuses being determined by, among other things, the spot size achievable by an energy input device (such as, for example, a laser) utilized to heat up and blow the fuses, as well as by the positional accuracy of the energy input device.
An exemplary fuse arrangement is shown in a semiconductor construction 10 of FIG. 1. The construction 10 comprises a substrate 12 and a plurality of electrical interconnects 14, 16, 18, 20, 22 and 24 provided across a surface of the substrate. The interconnects have fuses 26, 28, 30, 32, 34 and 36 associated therewith.
The fuses are separated from one another by a sufficient distance so that each fuse can be individually blown by energy from an energy input device. Additionally, the fuses are provided to be a sufficient distance from adjacent interconnects so that the adjacent interconnects are not adversely affected when a fuse is blown.
The fuses are typically grouped into one or more one-dimensional arrays (exemplary arrays are shown in construction 10, with one array being fuses 26, 28 and 30, and another being fuses 32, 34 and 36), and such arrays can be referred to as fuse “banks”. Each fuse bank has a footprint associated therewith, which corresponds to the amount of semiconductor real estate that must be set aside for the fuse bank. A continuing goal of semiconductor device processing is to increase the density of devices formed across a semiconductor substrate. Accordingly, it is a goal to reduce the footprint associated with fuse banks so that semiconductor real estate can be freed up for utilization in other devices.
A problem associated with the fuse bank arrangement of FIG. 1, in addition to the large amount of real estate consumed by the one-dimensional arrays of fuses, arises from the difficulty of exposing the fuses to sufficient energy to blow the fuses. Specifically, the fuses are formed at a common elevational level with the conductive interconnects 14, 16, 18, 20, 22 and 24. Typically, such conductive interconnects would be buried beneath several levels of dielectric material, and beneath a passivation layer capping the other levels of dielectric material. However, it can be difficult to provide sufficient energy through all the layers of dielectric material to consistently blow the fuses. Accordingly, it is common to etch a window over the fuses so that energy can be provided to blow the fuses. The etching of the window adds additional process steps to semiconductor fabrication, and generally it is desired to reduce the number of processing steps in order to increase throughput and reduce costs associated with a fabrication process. Additionally, the window can provide an avenue through which contaminants can undesirably migrate into a semiconductor construction.
For the above-described reasons, it is desirable to develop new arrangements of fuses for semiconductor constructions, and to develop methods of forming such arrangements.